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GS8330LW36C-250I 데이터시트(PDF) 10 Page - GSI Technology

부품명 GS8330LW36C-250I
상세설명  36Mb 誇1x1Lp CMOS I/O Late Write SigmaRAM
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제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
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GS8330LW36C-250I 데이터시트(HTML) 10 Page - GSI Technology

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Rev: 1.00 6/2003
10/30
© 2003, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8330LW36/72C-250/200
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
Programmable Enables
ΣRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at VDD,
E2 functions as an active high enable. If EP2 is held to VSS, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
SRAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic—
Σ1x1Lp
A
CK
E1
E2
E3
W
A0–An
CK
W
DQ0–DQn
Bank 0
Bank 1
Bank 2
Bank 3
Bank Enable Truth Table
EP2
EP3
E2
E3
Bank 0
VSS
VSS
Active Low
Active Low
Bank 1
VSS
VDD
Active Low
Active High
Bank 2
VDD
VSS
Active High
Active Low
Bank 3
VDD
VDD
Active High
Active High
E1
An – 1
An
A0–An – 2
An – 1
An
A0–An – 2
An – 1
An
A0–An – 2
An – 1
An
A0–An – 2
DQ
A
CK
E2
E3
W
DQ
A
CK
E2
E3
W
DQ
A
CK
E2
E3
W
DQ
E1
E1
E1
CQ
CQ
CQ
CQ
CQ
EP2
EP3
0
0
EP2
EP3
1
0
EP2
EP3
0
1
EP2
EP3
1
1


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