Preliminary

GS8662Q08/09/18/36E-300/250/200/167

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.01 9/2005

10/35

© 2005, GSI Technology

Special Functions

Byte Write and Nybble Write Control

Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with

a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be

stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low

during the data in sample times in a write sequence.

Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18

version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any

write sequence.

Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble

Write Enable” and “NBx” may be substituted in all the discussion above.

Example x18 RAM Write Sequence using Byte Write Enables

Data In Sample

Time

BW0

BW1

D0–D8

D9–D17

Beat 1

0

1

Data In

Don’t Care

Beat 2

1

0

Don’t Care

Data In

Resulting Write Operation

Byte 1

D0–D8

Byte 2

D9–D17

Byte 3

D0–D8

Byte 4

D9–D17

Written

Unchanged

Unchanged

Written

Beat 1

Beat 2

Output Register Control

SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output

Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the

output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K

and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to

function as a conventional pipelined read SRAM.