전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

GS81032AT-4I 데이터시트(PDF) 1 Page - GSI Technology

부품명 GS81032AT-4I
상세설명  32K x 32 1M Synchronous Burst SRAM
Download  23 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  GSI [GSI Technology]
홈페이지  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS81032AT-4I 데이터시트(HTML) 1 Page - GSI Technology

  GS81032AT-4I Datasheet HTML 1Page - GSI Technology GS81032AT-4I Datasheet HTML 2Page - GSI Technology GS81032AT-4I Datasheet HTML 3Page - GSI Technology GS81032AT-4I Datasheet HTML 4Page - GSI Technology GS81032AT-4I Datasheet HTML 5Page - GSI Technology GS81032AT-4I Datasheet HTML 6Page - GSI Technology GS81032AT-4I Datasheet HTML 7Page - GSI Technology GS81032AT-4I Datasheet HTML 8Page - GSI Technology GS81032AT-4I Datasheet HTML 9Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 23 page
background image
Rev: 1.01 7/2001
1/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81032AT/Q-150/138/133/117/100/66
32K x 32
1M Synchronous Burst SRAM
150 MHz–66 MHz
9 ns–18 ns
3.3 V VDD
3.3 V and 2.5 V I/O
TQFP, QFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP or QFP package
Functional Description
Applications
The GS81032A is a 1,048,576-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS81032A is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS81032A operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuit.
-150 -138 -133 -117 -100
-66
Unit
Pipeline
3-1-1-1
tCycle
tKQ
IDD
6.6
3.8
270
7.25
4
245
7.5
4
240
8.5
4.5
210
10
5
180
12.5
6
150
ns
ns
mA
Flow
Through
2-1-1-1
tCycle
tKQ
IDD
10.5
9
170
15
9.7
120
15
10
120
15
11
120
15
12
120
20
18
95
ns
ns
mA


유사한 부품 번호 - GS81032AT-4I

제조업체부품명데이터시트상세설명
logo
Vishay Siliconix
GS810C VISHAY-GS810C Datasheet
45Kb / 6P
   Microprocessor Reset Monitors
01-Nov-02
More results

유사한 설명 - GS81032AT-4I

제조업체부품명데이터시트상세설명
logo
Alliance Semiconductor ...
AS7C251MPFS32A ALSC-AS7C251MPFS32A Datasheet
522Kb / 19P
   2.5V 1M x 32/36 pipelined burst synchronous SRAM
AS7C331MPFS32A ALSC-AS7C331MPFS32A Datasheet
525Kb / 19P
   3.3V 1M x 32/36 pipelined burst synchronous SRAM
AS7C251MPFD32A ALSC-AS7C251MPFD32A Datasheet
522Kb / 19P
   2.5V 1M x 32/36 pipelined burst synchronous SRAM
AS7C331MPFD32A ALSC-AS7C331MPFD32A Datasheet
525Kb / 19P
   3.3V 1M x 32/36 pipelined burst synchronous SRAM
logo
List of Unclassifed Man...
GVT71128D32 ETC1-GVT71128D32 Datasheet
56Kb / 13P
   128K X 32 SYNCHRONOUS BURST SRAM
logo
Integrated Device Techn...
IDT71V432 IDT-IDT71V432 Datasheet
267Kb / 18P
   32K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect
logo
Alliance Semiconductor ...
AS7C251MPFS18A ALSC-AS7C251MPFS18A Datasheet
509Kb / 19P
   2.5V 1M x 18 pipelined burst synchronous SRAM
AS7C331MPFS18A ALSC-AS7C331MPFS18A Datasheet
509Kb / 19P
   3.3V 1M x 18 pipelined burst synchronous SRAM
AS7C251MFT18A ALSC-AS7C251MFT18A Datasheet
511Kb / 19P
   2.5V 1M x 18 flowthrough burst synchronous SRAM
AS7C331MPFD18A ALSC-AS7C331MPFD18A Datasheet
510Kb / 19P
   3.3V 1M x 18 pipelined burst synchronous SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com