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GS88018T-11I 데이터시트(PDF) 5 Page - GSI Technology |
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GS88018T-11I 데이터시트(HTML) 5 Page - GSI Technology |
5 / 25 page Rev: 1.11 8/2000 5/25 © 2000, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS88018/32/36T-11/11.5/100/80/66 TQFP Pin Description Pin Location Symbol Typ e Description 37, 36 A0, A1 I Address field LSBs and Address Counter preset Inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43 A2–A17 I Address Inputs 80 A18 I Address Inputs 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8 I/O Data Input and Output pins (x32, x36 Version) 51, 80, 1, 30 DQA9, DQB9, DQC9, DQD9 I/O Data Input and Output pins 51, 80, 1, 30 NC — No Connect (x32 Version) 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 DQA1–DQA9 DQB1–DQB9 I/O Data Input and Output pins 51, 52, 53, 56, 57 75, 78, 79, 1, 2, 3, 6, 7 25, 28, 29, 30 NC — No Connect 87 BW I Byte Write—Writes all enabled bytes; active low 93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low 95, 96 BC, BD I Byte Write Enable for DQC, DQD Data I/Os; active low (x32, x36 Version) 95, 96 NC — No Connect (x18 Version) 89 CK I Clock Input Signal; active high 88 GW I Global Write Enable—Writes all bytes; active low 98, 92 E1, E3 I Chip Enable; active low 97 E2 I Chip Enable; active high 86 G I Output Enable; active low 83 ADV I Burst address counter advance enable; active low 84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low 64 ZZ I Sleep Mode control; active high 14 FT I Flow Through or Pipeline mode; active low 31 LBO I Linear Burst Order mode; active low 15, 41, 65, 91 VDD I Core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS I I/O and Core Ground 4, 11, 20, 27, 54, 61, 70, 77 VDDQ I Output driver power supply 16, 38, 39, 42, 66 NC — No Connect |
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