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GS815036AGB-250 데이터시트(PDF) 1 Page - GSI Technology |
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GS815036AGB-250 데이터시트(HTML) 1 Page - GSI Technology |
1 / 25 page Product Preview GS815018/36AB-357/333/300/250 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 250 MHz–357 MHz 2.5 V VDD HSTL I/O 119-Bump BGA Commercial Temp Industrial Temp Rev: 1.05 10/2005 1/25 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Features • Register-Register Late Write mode, Pipelined Read mode • 2.5 V +200/–200 mV core power supply • 1.5 V or 1.8 V HSTL Interface • ZQ controlled programmable output drivers • Dual Cycle Deselect • Fully coherent read and write pipelines • Byte write operation (9-bit bytes) • Differential HSTL clock inputs, K and K • Asynchronous output enable • Sleep mode via ZZ • IEEE 1149.1 JTAG-compliant Serial Boundary Scan • JEDEC-standard 119-bump BGA package • Pb-Free 119-bump BGA package available Family Overview GS815018/36A are 18,874,368-bit (18Mb) high performance SRAMs. This family of wide, low voltage HSTL I/O SRAMs is designed to operate at the speeds needed to implement economical high performance cache systems. Functional Description Because GS815018/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. GS815018/36A support pipelined reads utilizing a rising-edge- triggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol. GS815018/36A are implemented with high performance technology and are packaged in a 119-bump BGA. Mode Control There are two mode control select pins (M1 and M2), which allow the user to set the correct read protocol for the design. The GS815018/36A support single clock Pipeline mode, which directly affects the two mode control select pins. In order for the part to fuction correctly, and as specified, M1 must be tied to VSS and M2 must be tied to VDD or VDDQ. This must be set at power-up and should not be changed during operation. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Parameter Synopsis -357 -333 -300 -250 Unit Pipeline Cycle tKHQV 2.8 1.4 3.0 1.5 3.3 1.6 4.0 2.0 ns ns Curr (x18) Curr (x36) 600 650 550 600 500 550 450 500 mA mA |
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