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AM42DL16X4D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 41 Page - SPANSION

๋ถ€ํ’ˆ๋ช… AM42DL16X4D
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM42DL16X4D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 41 Page - SPANSION

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Am42DL16x4D
January 9, 2002
P R E L IMINARY
AC CHARACTERISTICS
Flash Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 19 for test specifications.
Parameter
Description
Test Setup
Speed Options
Unit
JEDEC
Std
70
85
tAVAV
tRC
Read Cycle Time (Note 1)
Min
70
85
ns
t
AVQV
t
ACC
Address to Output Delay
CE#f, OE# = V
IL
Max
70
85
ns
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
Max
70
85
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
35
ns
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#f or
OE#, Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
tOH
tCE
Outputs
WE#
Addresses
CE#f
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 14.
Read Operation Timings


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