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AM42DL16X4D 데이터시트(HTML) 44 Page - SPANSION

부품명 AM42DL16X4D
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM42DL16X4D 데이터시트(HTML) 44 Page - SPANSION

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January 9, 2002
Am42DL16x4D
43
P R E L IMINARY
AC CHARACTERISTICS
Flash Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Parameter
Speed Options
Unit
JEDEC
Std
Description
Min
70
85
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
85
ns
t
AVWL
t
AS
Address Setup Time (WE# to Address)
Min
0
ns
t
ASO
Address Setup Time to OE# or
CE#f low during toggle bit
polling
Min
15
ns
tWLAX
tAH
Address Hold Time (WE# to Address)
Min
45
ns
t
AHT
Address Hold Time From CE#f or OE# high during toggle bit
polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
35
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
tOEH
OE# Hold Time
Read
Min
0
ns
Toggle and Data# Polling
Min
10
ns
tOEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write (OE# High to CE#f Low)
Min
0
ns
tGHWL
tGHWL
Read Recovery Time Before Write (OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time (CE#f to WE#)
Min
0
ns
tELWL
tCS
CE#f Setup Time (WE# to CE#f)
Min
0
ns
t
EHWH
t
WH
WE# Hold Time (CE#f to WE#)
Min
0
ns
tWHEH
tCH
CE#f Hold Time (CE#f to WE#)
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
30
35
ns
tELEH
tCP
CE#f Pulse Width
Min
30
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
0
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Typ
7
µs
tWHWH1
tWHWH1
Accelerated Programming Operation (Note 2)
Typ
4
µs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.7
sec
tVCS
VCCf Setup Time (Note 1)
Min
50
µs
t
RB
Write Recovery Time from RY/BY#
Min
0
ns
tBUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns


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