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AM42DL16X4D 데이터시트(HTML) 5 Page - SPANSION |
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4 Am42DL16x4D January 9, 2002 P R E L IMINARY Timing Diagram............................................................................... 49 Alternate CE#f Controlled Erase and Program Operations .... 50 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op- eration Timings................................................................................ 51 SRAM Read Cycle .................................................................. 52 Figure 28. SRAM Read Cycle—Address Controlled....................... 52 Figure 29. SRAM Read Cycle ......................................................... 53 SRAM Write Cycle .................................................................. 54 Figure 30. SRAM Write Cycle—WE# Control ................................. 54 Figure 31. SRAM Write Cycle—CE1#s Control .............................. 55 Figure 32. SRAM Write Cycle—UB#s and LB#s Control ................ 56 Flash Erase And Programming Performance . . 57 Flash Latchup Characteristics. . . . . . . . . . . . . . . 57 Package Pin Capacitance . . . . . . . . . . . . . . . . . . 57 FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 57 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 58 Figure 33. CE1#s Controlled Data Retention Mode....................... 58 Figure 34. CE2s Controlled Data Retention Mode......................... 58 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 59 FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm ............... 59 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 60 Revision A (October 24, 2001) ............................................... 60 |
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