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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM42DL16X4D 데이터시트(HTML) 53 Page - SPANSION |
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AM42DL16X4D 데이터시트(HTML) 53 Page - SPANSION |
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52 Am42DL16x4D January 9, 2002 P R E L IMINARY AC CHARACTERISTICS SRAM Read Cycle Note: CE1#s = OE# = V IL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL Figure 28. SRAM Read Cycle—Address Controlled Parameter Symbol Description Speed Options Unit 70 85 tRC Read Cycle Time Min 70 85 ns t AA Address Access Time Max 70 85 ns tCO1, tCO2 Chip Enable to Output Max 70 85 ns t OE Output Enable Access Time Max 35 45 ns tBA LB#s, UB#s to Valid Output Max 70 85 ns t LZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output Min 10 ns t BLZ UB#, LB# Enable to Low-Z Output Min 10 ns tOLZ Output Enable to Low-Z Output Min 5 ns tHZ1, tHZ2 Chip disable to High-Z Output Min 0 ns Max 25 tBHZ UB#s, LB#s Disable to High-Z Output Min 0 ns Max 25 tOHZ Output Disable to High-Z Output Min 0 ns Max 25 t OH Output Data Hold from Address Change Min 10 15 ns Address Data Out Previous Data Valid Data Valid tAA tRC tOH |
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