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AM42DL16X4D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 9 Page - SPANSION

๋ถ€ํ’ˆ๋ช… AM42DL16X4D
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM42DL16X4D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 9 Page - SPANSION

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Am42DL16x4D
January 9, 2002
P R E L IMINARY
PIN DESCRIPTION
A17โ€“A0
= 18 Address Inputs (Common)
Aโ€“1, A19โ€“A18 = 3 Address Inputs (Flash)
DQ15โ€“DQ0
= 16 Data Inputs/Outputs (Common)
CE#f
= Chip Enable (Flash)
CE#s
= Chip Enable (SRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (SRAM)
LB#s
= Lower Byte Control (SRAM)
CIOf
= I/O Configuration (Flash)
CIOf = V
IH = Word mode (x16),
CIOf = V
IL = Byte mode (x8)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CCf
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CCs
= SRAM Power Supply
V
SS
= Device Ground (Common)
NC
= Pin Not Connected Internally
LOGIC SYMBOL
18
16 or 8
DQ15โ€“DQ0
A0โ€“A17
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
Aโ€“1, A18โ€“A19
LB#s
CIOf
CE1#s
CE2s


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