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AM42DL16X4D 데이터시트(HTML) 23 Page - SPANSION

부품명 AM42DL16X4D
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM42DL16X4D 데이터시트(HTML) 23 Page - SPANSION

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Am42DL16x4D
January 9, 2002
P R E L IMINARY
Table 11.
System Interface String
Table 12.
Device Geometry Definition
Addresses
(Word Mode)
Data
Description
1Bh
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
V
CC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
V
PP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0004h
Typical timeout per single byte/word write 2
N µs
20h
0000h
Typical timeout for Min. size buffer write 2
N µs (00h = not supported)
21h
000Ah
Typical timeout per individual block erase 2
N ms
22h
0000h
Typical timeout for full chip erase 2
N ms (00h = not supported)
23h
0005h
Max. timeout for byte/word write 2
N times typical
24h
0000h
Max. timeout for buffer write 2
N times typical
25h
0004h
Max. timeout per individual block erase 2
N times typical
26h
0000h
Max. timeout for full chip erase 2
N times typical (00h = not supported)
Addresses
(Word Mode)
Data
Description
27h
0016h
Device Size = 2
N byte
28h
29h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information


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