CS5828
page 4 of 13
FUNCTIONAL DESCRIPTION
Control logic
There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are
controlled by the control signal “SHTDN”. If SHTDN is high, the circuit is in the normal mode, else if low, the
circuit is in the power down mode. In the power down mode, every block is off to make sure the least power
consumption.
7 x CLK PLL
7 x CLK PLL, which is a phase lock loop, generates seven times clock of CKIN. The signal “RF” indicates that the
input data (D0 ~ D27) is rising edge or falling edge trigger by CKIN. If RF=1, it is rising edge trigger, else if RF=0,
it is falling trigger. This seven times clock of CKIN is used by the Parallel ~ LOAD 7 Bit shift Register. 7 x CLK PLL
also generate the control signal “SHIFT/LOAD”. This signal is also used by the Parallel ~ LOAD 7 Bit Shift
Register to indicate when to load data or shift data.
Parallel ~ LOAD 7 Bit shift Register
This block transfers 7 bits parallel data into one bit series data out. It is controlled by SHIFT/LOAD. If this control
signal is low, the data are loaded into shift registers. Next, the SHIFT/LOAD turns high to shift data from shift
register to output buffer seven times. One load and then seven shift.
Ref:
There are two properties in this block. One is that it supports reference voltage to fine the output’s common mode
voltage. Another is that it generates about (4ns ~6ns) pulse width’s power on reset signal. When power on, all
block would be reset by power on reset signal to make sure that the circuit would not stuck-at some situation we
do not care.
Output buffer
There are four data output buffers and one clock output buffer. Output buffer generates differential pair output
that swing is under 500 ~ 900mV, and common-mode voltage is under 1.125V ~ 1.375V.
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