Philips Semiconductors

Product specification

74ABT833

Octal transceiver with parity generator/checker

(3-State)

1993 Jun 21

3

LOGIC SYMBOL

OEB

OEA

CLEAR

14

1

11

15

10

PARITY

ERROR

CP

13

23

45

67

89

A0 A1 A2 A3 A4 A5 A6 A7

B0 B1 B2 B3 B4 B5 B6 B7

23 22 21 20 19 18 17 16

SA00213

FUNCTION TABLE

INPUTS

OUTPUTS

MODE

OEB

OEA

An

Σ of Highs

Bn + Parity

Σ of Highs

An

Bn

PARITY

A data to B bus and generate odd parity

output

L

H

Odd

Even

(output)

(input)

An

L

H

H

L

(output)

X

Bn

(input)

(input)

H

H

X

X

Z

Z

Z

A data to B bus and generate inverted

parity output

L

L

Odd

Even

(output)

(input)

An

H

L

NOTES:

1. Error checking is detailed in the Error Flag Function Table below.

2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.

ERROR FLAG FUNCTION TABLE

INPUTS

Internal node

Output

MODE

CLEAR

CP

Bn + Parity

Σ of Highs

Point ”P”

Pre–state

ERRORn–1

ERROR

OUTPUT

Sample

H

H

H

↑

↑

X

Odd

Even

X

H

L

X

H

X

L

H

L

L

Hold

H

↑

X

X

X

NC

Clear

L

X

X

X

X

H

H

= High voltage level steady state

L

= Low voltage level steady state

X

= Don’t care

NC = No change

Z

= High impedance ”off” state

↑

= Low-to-High clock transition

↑

= Not a Low-to-High clock transition