전자부품 데이터시트 검색엔진 |
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74AHCT74PW 데이터시트(PDF) 10 Page - NXP Semiconductors |
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74AHCT74PW 데이터시트(HTML) 10 Page - NXP Semiconductors |
10 / 20 page 1999 Sep 23 10 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 Type 74AHCT74 GND = 0 V; tr =tf ≤ 3.0 ns. Note 1. Typical values at VCC = 5.0 V. SYMBOL PARAMETER TEST CONDITIONS Tamb (°C) UNIT WAVEFORMS CL 25 −40 to +85 −40 to +125 MIN. TYP. MAX. MIN. MAX. MIN. MAX. VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 15 pF − 3.3 7.8 1.0 9.0 1.0 10.0 ns propagation delay nSD nRD to nQ, nQ see Figs 7 and 8 − 3.7 10.4 1.0 12.0 1.0 13.0 ns fmax maximum clock pulse frequency 100 160 − 80 − 80 − ns tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 50 pF − 4.8 8.8 1.0 10.0 1.0 11.0 ns propagation delay nSD nRD to nQ, nQ see Figs 7 and 8 − 5.3 11.4 1.0 13.0 1.0 14.5 ns tW clock pulse width HIGH or LOW see Figs 6 and 8 5.0 −− 5.0 − 5.0 − ns tW(st)(rst) set or reset pulse width LOW see Figs 7 and 8 5.0 −− 5.0 − 5.0 − ns trem removal time set or reset 3.5 −− 3.5 − 3.5 − ns tsu set-up time nD to nCP see Figs 6 and 8 5.0 −− 5.0 − 5.0 − ns th hold time nD to nCP 0 −− 0 − 0 − ns fmax maximum clock pulse frequency 80 140 − 65 − 65 − ns |
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유사한 설명 - 74AHCT74PW |
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