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74ALVT16652DGG 데이터시트(PDF) 4 Page - NXP Semiconductors |
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74ALVT16652DGG 데이터시트(HTML) 4 Page - NXP Semiconductors |
4 / 14 page Philips Semiconductors Product specification 74ALVT16652 2.5V/3.3V 16-bit bus transceiver/register (3-State) 1998 Feb 13 4 LOGIC DIAGRAM 1D C1 Q DETAIL A X 7 nB0 1D C1 Q nA0 1of 8 Channels nA7 nA6 nA5 nA4 nA3 nA2 nA1 nB1 nB2 nB3 nB4 nB5 nB6 nB7 nOEBA nOEAB nCPBA nSBA nCPAB nSAB SH00065 FUNCTION TABLE INPUTS DATA I/O OPERATING MODE nOEAB nOEBA nCPAB nCPBA nSAB nSBA nAx nBx OPERATING MODE L L H H H or L ↑ H or L ↑ X X X X Input Input Isolation Store A and B data X H H H ↑ ↑ H or L ↑ X ** X X Input Unspecified output* Store A, Hold B Store A in both registers L L X L H or L ↑ ↑ ↑ X X X ** Unspecified output* Input Hold A, Store B Store B in both registers L L L L X X X H or L X X L H Output Input Real time B data to A bus Stored B data to A bus H H H H X H or L X X L H X X Input Output Real time A data to B bus Store A data to B bus H L H or L H or L H H Output Output Stored A data to B bus Stored B data to A bus H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High clock transition * The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock. ** If both Select controls (nSAB and nSBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be staggered in order to load both registers. |
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