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75V16F64GS16 데이터시트(HTML) 36 Page - Integrated Silicon Solution, Inc

부품명 75V16F64GS16
상세내용  64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP)
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제조사  ISSI [Integrated Silicon Solution, Inc]
홈페이지  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

75V16F64GS16 데이터시트(HTML) 36 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
08/01/02
75V16F64GS16
ISSI®
PSRAM WRTE OPERATIONS
Value
Parameter
Symbol
Min.
Max.
Unit
Write Cycle Time(1)
tWC
90
ns
Address Setup Time(2)
tAS
0—
ns
Address Setup Timev
tAH
45
ns
CE1r Write Setup Time
tCS
0
1000
ns
CE1r Write Hold Time
tCH
0
1000
ns
WE Setup Time
tWS
0—
ns
WE Hold Time
tWH
0—
ns
LB adnd UB Setup Time
tBS
0—
ns
LB adnd UB Hold Time
tBH
-5
ns
OE Setup Time(3)
tOES
0
1000
ns
OE Hold Time(3,4)
tOEH
45
1000
ns
OE Hold Time(5)
tOEH(ABS)20
ns
OE High to CE1r Low Setup Time(6)
tOHCL
-3
ns
OE High to Address Hold Time(7)
tOHAH
-5
ns
CE1r Write Pulse Width(1,8)
tCW
60
ns
WE Write Pulse Width(1,8)
tWP
60
ns
CE1r Write Recovery Time(1,9)
tWRC
15
ns
WE Write Recovery Time(1,3,9)
tWR
15
1000
ns
Data Setup Time
tDS
20
ns
Data Hold Time
tDH
0—
ns
CE1r High Pulse Width(9)
tCD
20
ns
Notes:
1. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) .
2. New write address is valid from either
CE1r or WE that is brought to High.
3. Maximum value is applicable if
CE1r is kept at Low and both WE and OE are kept at High.
4. The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
5. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by
WE and CE1r stay Low.
6. tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case
OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1r Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
7. Applicable if
CE1r stays Low after read operation.
8. tCW and tWP are applicable if write operation is initiated by
CE1r and WE, respectively.
9. tWRC and tWR are applicable if write operation is terminated by
CE1r and WE, respectively.
The tWR (Min) can be ignored if
CE1r is brought to High together or after WE is brought to High.
In such a case, the tCP (Min) must be satisfied.


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