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75V16F64GS16 데이터시트(HTML) 47 Page - Integrated Silicon Solution, Inc

부품명 75V16F64GS16
상세내용  64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP)
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제조사  ISSI [Integrated Silicon Solution, Inc]
홈페이지  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

75V16F64GS16 데이터시트(HTML) 47 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
47
PRELIMINARY INFORMATION
Rev. 00A
08/01/02
75V16F64GS16
ISSI®
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
VDR
Vccr Data Retention Supply Voltage
CE1r = CE2r
≥ VCCr -0.2V OR,
2.1
3.1
V
CE1r = CE2r = VIH
IDR
Vccr Data Retention Supply Current
2.3 V
≤ VCCr ≤ 2.7 V,
—1
mA
VIN
= VIH (1) or VIL
CE1r = CE2r
= VIH (1),
IOUT = 0 MA
IDR1
Vccr Data Retention Supply Current
2.3 V
≤VCCr ≤ 2.7 V,
—70
µA
VIN
≤ 0.2 V or VIN ≥ VCCr -2.0 V,
CE1r = CE2r
≥ VCCr -0.2 V
IOUT = 0 MA
tDRS
Data Retention SetupTime
2.7 V
≤ VCCr ≤ 3.1 V,
0—
ns
At Data Retention Entry
tDRR
Data Retention RecoveryTime
2.7 V
≤ VCCr ≤ 3.1 V,
90
ns
After Data Retention
∆V/∆t
VCCR Voltage Transition Time
0.5
V/µs
Note:
1. 2.0 V
≤ VIN ≤ VCCr + 0.3
PSRAM DATA RETENTION TIMING
Note:
1. 2.0 V
VIH VCCr + 0.3 V
3.1V
2.7V
2.3V
4.0V
GND
tDRS
tDRR
Vccr
CE2r
CE1r
CE1r = CE2r >Vccr - 0.2V or
VIH(1) Min
Data Retention Mode
Data bus must be in High-Z at data retention entry
∆V/∆t
∆V/∆t


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