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AM42DL640AG 데이터시트(HTML) 4 Page - SPANSION

부품명 AM42DL640AG
상세내용  Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only
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AM42DL640AG 데이터시트(HTML) 4 Page - SPANSION

 
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October 22, 2002
Am42DL640AG
3
PR E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
IH; . 10
Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V
SS ....11
Word/Byte Configuration ........................................................ 11
Requirements for Reading Array Data ................................... 12
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 12
Simultaneous Read/Write Operations with Zero Latency ....... 12
Standby Mode ........................................................................ 12
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13
Table 3. Am29DL640G Sector Architecture ....................................14
Table 4. Bank Address ....................................................................17
Table 5. SecSi
 Sector Addresses ...............................................17
Sector/Sector Block Protection and Unprotection .................. 18
Table 6. Am29DL640G Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................18
Write Protect (WP#) ................................................................ 18
Table 7. WP#/ACC Modes ..............................................................19
Temporary Sector Unprotect .................................................. 19
Figure 1. Temporary Sector Unprotect Operation........................... 19
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 20
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 21
Figure 3. SecSi Sector Protect Verify.............................................. 22
Hardware Data Protection ...................................................... 22
Low V
CC Write Inhibit ........................................................... 22
Write Pulse “Glitch” Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 8. CFI Query Identification String .......................................... 23
System Interface String................................................................... 23
Table 10. Device Geometry Definition ............................................ 24
Table 11. Primary Vendor-Specific Extended Query ...................... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ..
26
Byte/Word Program Command Sequence ............................. 27
Unlock Bypass Command Sequence .................................. 27
Figure 4. Program Operation .......................................................... 28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
Figure 5. Erase Operation............................................................... 29
Table 12. Am29DL640G Command Definitions .............................. 30
Write Operation Status . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ................................................................. 31
Figure 6. Data# Polling Algorithm .................................................. 31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 7. Toggle Bit Algorithm........................................................ 32
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 13. Write Operation Status ................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 8. Maximum Negative Overshoot Waveform ...................... 35
Figure 9. Maximum Positive Overshoot Waveform........................ 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
CMOS Compatible .................................................................. 36
SRAM DC and Operating Characteristics . . . . . 37
Figure 10. I
CC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 38
Figure 11. Typical I
CC1 vs. Frequency ............................................ 38
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Test Setup.................................................................... 39
Figure 13. Input Waveforms and Measurement Levels ................. 39
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
SRAM CE#s Timing ................................................................ 40
Figure 14. Timing Diagram for Alternating
Between SRAM to Flash ................................................................ 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Flash Read-Only Operations ................................................. 41
Figure 15. Read Operation Timings ............................................... 41
Hardware Reset (RESET#) .................................................... 42
Figure 16. Reset Timings ............................................................... 42
Word/Byte Configuration (CIOf) .............................................. 43
Figure 17. CIOf Timings for Read Operations................................ 43
Figure 18. CIOf Timings for Write Operations................................ 43
Erase and Program Operations .............................................. 44
Figure 19. Program Operation Timings.......................................... 45
Figure 20. Accelerated Program Timing Diagram.......................... 45
Figure 21. Chip/Sector Erase Operation Timings .......................... 46
Figure 22. Back-to-back Read/Write Cycle Timings ...................... 47
Figure 23. Data# Polling Timings (During Embedded Algorithms). 47
Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 48
Figure 25. DQ2 vs. DQ6................................................................. 48
Temporary Sector Unprotect .................................................. 49
Figure 26. Temporary Sector Unprotect Timing Diagram .............. 49
Figure 27. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 50
Alternate CE#f Controlled Erase and Program Operations .... 51
Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 52
SRAM Read Cycle .................................................................. 53
Figure 29. SRAM Read Cycle—Address Controlled...................... 53
Figure 30. SRAM Read Cycle ........................................................ 54
SRAM Write Cycle .................................................................. 55
Figure 31. SRAM Write Cycle—WE# Control ................................ 55
Figure 32. SRAM Write Cycle—CE1#s Control ............................. 56
Figure 33. SRAM Write Cycle—UB#s and LB#s Control ............... 57
Flash Erase And Programming Performance . . 58


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