© 2002 QuickLogic Corporation
www.quicklogic.com
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Device Highlights
High Performance & High Density
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58,000 Usable PLD Gates with 252 I/Os
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300 MHz 16-bit Counters, 400 MHz
Datapaths, 160+ MHz FIFOs
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0.35
µm four-layer metal non-volatile
CMOS process for smallest die sizes
High Speed Embedded SRAM
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18 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
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5 ns access times, each port independently
accessible
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Fast and efficient for FIFO, RAM, and ROM
functions
Easy to Use / Fast Development
Cycles
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100% routable with 100% utilization and
complete pin-out stability
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Variable-grain logic cells provide high
performance and 100% utilization
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Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
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Interfaces with both 3.3 V and 5.0 V devices
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PCI compliant with 3.3 V and 5.0 V busses
for -1/-2/-3/-4 speed grades
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Full JTAG boundary scan
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I/O Cells with individually controlled
Registered Input Path and Output Enables
Figure 1: QuickRAM Block Diagram
18
RAM
Blocks
1,008
High Speed
Logic Cells
Interface
QL4058 QuickRAM Data Sheet
58,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
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