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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WV3HG64M64EEU403D4ISG 데이터시트(PDF) 7 Page - White Electronic Designs Corporation |
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WV3HG64M64EEU403D4ISG 데이터시트(HTML) 7 Page - White Electronic Designs Corporation |
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7 / 11 page  WV3HG64M64EEU-D4 May 2006 Rev. 2 ADVANCED 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC TIMING PARAMETERS & SPECIFICATIONS AC CHARACTERISTICS 665 534 403 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNIT CL = 5 tCK (5) 3,000 8,000 ps CL = 4 tCK (4) 3,750 8,000 3,750 8,000 5,000 8,000 ps CL = 3 tCK (3) 5,000 8,000 5,000 8,000 5,000 8,000 ps CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK Half clock period tHP MIN (tCH, tCL) MIN (tCH, tCL) MIN (tCH, tCL) ps Clock jitter tJIT 250 250 250 ps DQ output access time from CK/CK# tAC -450 +450 -500 +500 -600 +600 ps Data-out high-impedance window from CK/CK# tHZ tAC MAX tAC MAX tAC MAX ps Data-out low-impedance window from CK/CK# tLZ tAC MIN tAC MAX tAC MIN tAC MAX tAC MIN tAC MAX ps DQ and DM input setup time relative to DQS tDS 100 100 150 ps DQ and DM input hold time relative to DQS tDH 225 225 275 ps DQ and DM input pulse width (for each input) tDIPW 0.35 0.35 0.35 tCK Data hold skew factor tQHS 340 400 450 ps DQ…DQS hold, DQS to first DQ to go nonvalid, per access tQH tHP - tQHS tHP - tQHS tHP - tQHS ps Data valid output window (DVW) tDVW tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK DQS output access time from CK/CK# tDQSCK -400 +400 -450 +450 -500 +500 ps DQS falling edge to CK rising … setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising … hold time tDSH 0.2 0.2 0.2 tCK DQS…DQ skew, DQS to last DQ valid, per group, per access tDQSQ 240 300 350 ps DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS write preamble setup time tWPRES 000 p s DQS write preamble tWPRE 0.35 0.35 0.35 tCK DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK Address and control input pulse width for each input tIPW 0.6 0.6 0.6 tCK Address and control input setup time tIS 200 250 350 ps Address and control input hold time tIH 275 375 475 ps Address and control input hold time tCCD 222 tCK Note: AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page |
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