74HC563 datasheet(2/7 Pages) PHILIPS

부품명	74HC563

상세설명	Octal D-type transparent latch; 3-state; inverting

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제조업체	PHILIPS [NXP Semiconductors]

홈페이지	http://www.nxp.com

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2 / 7 page

December 1990

2

Philips Semiconductors

Product speciﬁcation

Octal D-type transparent latch; 3-state;

inverting

74HC/HCT563

FEATURES

• 3-state inverting outputs for bus

oriented applications

• Inputs and outputs on opposite

sides of package allowing easy

interface with microprocessor

• Common 3-state output enable

input

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT563 are high-speed

Si-gate CMOS devices and are pin

compatible with low power Schottky

TTL (LSTTL). They are specified in

compliance with JEDEC standard no.

7A.

The 74HC/HCT563 are octal D-type

transparent latches featuring

separate D-type inputs for each latch

and inverting 3-state outputs for bus

oriented applications.

A latch enable (LE) input and an

output enable (OE) input are common

to all latches.

The “563” is functionally identical to

the “573”, but has inverted outputs.

The “563” consists of eight D-type

transparent latches with 3-state

inverting outputs. The LE and OE are

common to all latches.

When LE is HIGH, data at the Dn

inputs enter the latches. In this

condition the latches are transparent,

i.e. a latch output will change state

each time its corresponding D-input

changes.

When LE is LOW the latches store the

information that was present at the

D-inputs a set-up time preceding the

HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the

8 latches are available at the outputs.

When OE is HIGH, the outputs go to

the high impedance OFF-state.

Operation of the OE input does not

affect the state of the latches.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

for HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

tPHL/ tPLH

propagation delay Dn, LE to Qn

CL = 15 pF; VCC =5 V

14

16

ns

CI

input capacitance

3.5

pF

CPD

power dissipation capacitance per latch

notes 1 and 2

19

pF

유사한 부품 번호 - 74HC563

제조업체	부품명	데이터시트	상세설명
NXP Semiconductors	74HC563N	67Kb / 7P	Octal D-type transparent latch 3-state inverting December 1990

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유사한 설명 - 74HC563

제조업체	부품명	데이터시트	상세설명
NXP Semiconductors	74HC563N	67Kb / 7P	Octal D-type transparent latch 3-state inverting December 1990
NXP Semiconductors	74HC533	62Kb / 7P	Octal D-type transparent latch; 3-state; inverting December 1990
Integral Corp.	IN74ACT533	195Kb / 5P	OCTAL 3-STATE INVERTING TRANSPARENT LATCH
KODENSHI_AUK CORP.	KK74HC533A	279Kb / 7P	Octal 3-State Inverting Transparent Latch
ON Semiconductor	MC74HC373A	195Kb / 8P	Octal 3-State Non-Inverting Transparent Latch March, 2000 ??Rev. 8
Motorola, Inc	MC54-74HC373A	202Kb / 8P	Octal 3-State Non-Inverting Transparent Latch
ON Semiconductor	MC74HC373A	122Kb / 7P	Octal 3-State Non-Inverting Transparent Latch August, 2014 ??Rev. 15
System Logic Semiconduc...	SL74LV373	47Kb / 8P	OCTAL D-TYPE TRANSPARENT LATCH(3-State)
System Logic Semiconduc...	SL74LV573	43Kb / 6P	OCTAL D-TYPE TRANSPARENT LATCH (3-State)
NXP Semiconductors	74ALVC373	97Kb / 20P	Octal D-type transparent latch 3-state 2002 Feb 26

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74HC563 데이터시트(PDF) 2 Page - NXP Semiconductors

74HC563 데이터시트(HTML) 2 Page - NXP Semiconductors

유사한 부품 번호 - 74HC563

유사한 설명 - 74HC563

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