전자부품 데이터시트 검색엔진 |
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AD5628 데이터시트(PDF) 9 Page - Analog Devices |
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AD5628 데이터시트(HTML) 9 Page - Analog Devices |
9 / 24 page Preliminary Technical Data AD5628/AD5648/AD5668 Rev. PrA| Page 9 of 24 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. (VDD = +2.7 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted) Limit at TMIN, TMAX Parameter VDD = 2.7 V to 3.6 V VDD= 3.6 V to 5.5 V Unit Conditions/Comments t1 1 20 20 ns min SCLK Cycle Time t2 11 9 ns min SCLK High Time t3 9 9 ns min SCLK Low Time t4 13 13 ns min SYNC to SCLK Falling Edge Setup Time t5 4 4 ns min Data Setup Time t6 4 4 ns min Data Hold Time t7 0 0 ns min SCLK Falling Edge to SYNC Rising Edge t8 25 20 ns min Minimum SYNC High Time t9 13 13 ns min SYNC Rising Edge to SCLK Fall Ignore t10 0 0 ns min SCLK Falling Edge to SYNC Fall Ignore t11 20 20 ns min LDAC Pulsewidth Low t12 20 20 ns min SCLK Falling Edge to LDAC Rising Edge t13 20 20 ns min /CLR Pulse Width Low t14 0 0 ns min SCLK Falling Edge to LDAC Falling Edge t15 tbd tbd ns min /CLR Pulse Activation Time (AD5380?) t4 t3 SCLK SYNC DIN t1 t2 t5 t6 t7 t8 DB31 DB0 t9 t10 t11 t12 LDAC1 LDAC2 t14 NOTES 1. ASYNCHRONOUS LDAC UPDATE MODE. 2. SYNCHRONOUS LDAC UPDATE MODE. t13 CLR Figure 2. Serial Write Operation 1 3Maximum SCLK frequency is 50 MHz at VDD = +2.7 V to +5.5 V |
유사한 부품 번호 - AD5628 |
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유사한 설명 - AD5628 |
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