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74LVC2952ADB 데이터시트(PDF) 6 Page - NXP Semiconductors |
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74LVC2952ADB 데이터시트(HTML) 6 Page - NXP Semiconductors |
6 / 11 page Philips Semiconductors Product specification 74LVC2952A Octal registered tranceiver with 5-volt tolerant inputs/ouputs (3-State) 1998 Jul 29 6 AC WAVEFORMS VM = 0.6 V at VCC = 1.2 V VM = 1.0 V at VCC = 2.0 V VM = 1.5 V at VCC = 3.0 V VOL and VOH are the typical output voltage drop that occur with the 3-State output load. SV01720 GND VOL VI VOH An, Bn OUTPUT VM CPXX INPUT VM tPLH tPHL 1/fmax tW Figure 1. Clock input (CPBA, CPAB) to output (Bn, An) propagation delays, the clock pulse width and the maximum clock frequency. SV01721 VM An, Bn, CEnn INPUT CPXX INPUT VM tsu tsu th th GND GND VI VI Figure 2. Set-up and hold times for the An, Bn and CEnn inputs. NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance SV01722 GND VI VCC VX VY outputs disabled outputs enabled outputs enabled tPHZ tPZH tPZL tPLZ VOL VOH GND VM VM VM CPXX INPUT OUTPUT LOW–to–OFF OFF–to–LOW OUTPUT HIGH-to-OFF OFF-to-HIGH Figure 3. 3-State enable and disable times. TEST CIRCUIT PULSE GENERATOR VI RT D.U.T. VO CL 50pF S1 2 x VCC Open GND 500 Ω 500 Ω VCC VI t 2.7V VCC 2.7V – 3.6V 2.7V Test S1 GND tPLZ/tPZL 2 x VCC tPHZ/tPZH tPLH/tPHL Open SY00003 VCC Figure 4. Load circuitry for switching times. |
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