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74LVC74ADB 데이터시트(PDF) 5 Page - NXP Semiconductors

부품명 74LVC74ADB
상세설명  Dual D-type flip-flop with set and reset; positive-edge trigger
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Dual D-type flip-flop with set and reset;
positive-edge trigger
Philips Semiconductors
Product Specification
74LVC74A
1998 Jun 17
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
°C to +85°C
UNIT
MIN
TYP1
MAX
V
HIGH level Input voltage
VCC = 1.2V
VCC
V
VIH
HIGH level Input voltage
VCC = 2.7 to 3.6V
2.0
V
V
LOW level Input voltage
VCC = 1.2V
GND
V
VIL
LOW level Input voltage
VCC = 2.7 to 3.6V
0.8
V
VCC = 2.7V; VI = VIH or VIL; IO = –12mA
VCC*0.5
VO
HIGH level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = –100µA
VCC*0.2
VCC
V
VOH
HIGH level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = –18mA
VCC*0.6
V
VCC = 3.0V; VI = VIH or VIL; IO = –24mA
VCC*1.0
VCC = 2.7V; VI = VIH or VIL; IO = 12mA
0.40
VOL
LOW level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = 100µA
GND
0.20
V
VCC = 3.0V; VI = VIH or VIL; IO = 24mA
0.55
I
Input leakage current
V
=3 6V; V = 5 5V or GND
"01
"5
µA
II
Input leakage current
VCC = 3.6V; VI = 5.5V or GND
"0.1
"5
µA
ICC
Quiescent supply current
VCC = 3.6V; VI = VCC or GND; IO = 0
0.1
10
µA
∆ICC
Additional quiescent supply current per
input pin
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0
5
500
µA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = –40_C to +85_C
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3V ±0.3V
VCC = 2.7V
UNIT
MIN
TYP1
MAX
MIN
MAX
Propagation delay
nCP to nQ, nQ
Figures 1, 3
1.5
3.6
5.2
6.0
ns
tPHL/
tPLH
Propagation delay
nSD to nQ, nQ
Figures 2, 3
1.5
3.5
5.4
6.4
ns
Propagation delay
nRD to nQ, nQ
Figures 2, 3
1.5
3.5
5.4
6.4
ns
tW
Clock pulse width HIGH or LOW
Figure 1
3.3
1.3
ns
tW
Set or reset pulse width LOW
Figure 2
3.3
1.7
ns
trem
Removal time set or reset
Figure 2
1
–3
ns
tsu
Set-up time nD to nCP
Figure 1
2.0
0.8
ns
th
Hold time nD to nCP
Figure 1
1
–0.7
ns
fmax
Maximum clock pulse frequency
Figure 1
150
250
MHz
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.


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