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74LVC821APW 데이터시트(PDF) 2 Page - NXP Semiconductors |
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2 / 12 page Philips Semiconductors Product specification 74LVC821A 10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger (3-State) 2 1998 Sep 25 853-1970 20088 FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDEC standard no. 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface with TTL levels • 10-bit positive edge-triggered register • Independent register and 3-State buffer operation • Flow-through pin-out architecture DESCRIPTION The 74LVC821A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5.0V devices. In 3-state operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC821A is a10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The ten flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the ten flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay CP to Qn CL = 50 pF; V 33 V 5.4 ns fmax Maximum clock frequency VCC = 3.3 V 150 MHz CI Input capacitance 5.0 pF CPD Power dissipation capacitance per flip-flop Notes 1 and 2 26 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDERING CODE PKG. DWG. # 24-Pin Plastic SO –40 °C to +85°C 74LVC821A D SOT137-1 24-Pin Plastic SSOP Type II –40 °C to +85°C 74LVC821A DB SOT340-1 24-Pin Plastic TSSOP Type I –40 °C to +85°C 74LVC821A PW SOT355-1 |
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