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74LVC823ADB 데이터시트(PDF) 8 Page - NXP Semiconductors

부품명 74LVC823ADB
상세설명  9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC823ADB 데이터시트(HTML) 8 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC823A
9-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
1998 Sep 24
8
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V
GND
VOL
VI
VOH
VM
CP INPUT
QnOUTPUT
VM
tPLH
tPHL
1/fmax
tW
SA00423
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency.
outputs
disabled
outputs
enabled
outputs
enabled
tPHZ
tPZH
tPZL
tPLZ
VX
VY
VM
VM
VM
OE INPUT
VCC
VI
VOL
VOH
GND
GND
OUTPUT
LOW–to–OFF
OFF–to–LOW
OUTPUT
HIGH–to–OFF
OFF–to–HIGH
SA00424
Figure 2. 3-State enable and disable times.
VM
Dn,
INPUT
Qn OUTPUT
VM
th
tsu
th
tsu
VM
CP INPUT
GND
GND
VOL
VI
VI
VOH
SA00425
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
CE
Figure 3. Data setup and hold times for the Dn input and CE
input to the CP input.
SA00519
tPHL
trem
Qn OUTPUT
MR INPUT
CP INPUT
tw
Figure 4. Master reset pulse width, master reset to clock
removal time, master reset to output propagation delay.
TEST CIRCUIT
PULSE
GENERATOR
VI
RT
D.U.T.
VO
CL
50pF
S1
2 x VCC
Open
GND
500
500
VCC
VI
t 2.7V
VCC
2.7V – 3.6V
2.7V
Test
S1
GND
tPLZ/tPZL
2 x VCC
tPHZ/tPZH
tPLH/tPHL
Open
SY00003
VCC
Figure 5. Load circuitry for switching times.


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