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DS3903 데이터시트(PDF) 10 Page - Maxim Integrated Products |
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DS3903 데이터시트(HTML) 10 Page - Maxim Integrated Products |
10 / 11 page Triple 128-Position Nonvolatile Digital Potentiometer 10 _____________________________________________________________________ The following bus protocol has been defined: Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as con- trol signals. Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain high. Start Data Transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data Valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS3903 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the com- mand/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The mas- ter returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge can be returned. The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. The DS3903 can operate in the following three modes: 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is trans- mitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit has been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3903 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. 3) Slave Address: Command/control byte is the first byte received following the start condition from the master device. The command/control byte consists of a 6-bit control code. For the DS3903, this is set as 101000 binary for read/write operations. The next bit of the command/control byte is the device select bit or slave address (A0). It is used by the master device to select which of two devices is to be accessed. When reading or writing the DS3903, the device-select bits must match the device-select pin (A0). The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a ‘1’, a read operation is selected, and when set to a ‘0’, a write operation is selected. Following the start condition, the DS3903 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 101000 control code, |
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