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74LVT125PW 데이터시트(PDF) 1 Page - NXP Semiconductors |
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74LVT125PW 데이터시트(HTML) 1 Page - NXP Semiconductors |
1 / 10 page 1. General description The LVT125 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device combines low static and dynamic power dissipation with high speed and high output drive. The 74LVT125 device is a quad buffer that is ideal for driving bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one of the 3-state outputs. 2. Features s Quad bus interface s 3-state buffers s Output capability: +64 mA and −32 mA s TTL input and output switching levels s Input and output interface capability to systems at 5 V supply s Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion and extraction permitted s No bus current loading when output is tied to 5 V bus s Power-up 3-state s Latch-up protection: x JESD78: exceeds 500 mA s ESD protection: x MIL STD 883 method 3015: exceeds 2000 V x Machine model: exceeds 200 V 3. Quick reference data 74LVT125 3.3 V quad buffer; 3-state Rev. 05 — 10 February 2005 Product data sheet Table 1: Quick reference data GND = 0 V; Tamb =25 °C. Symbol Parameter Conditions Min Typ Max Unit tPLH propagation delay nA to nY CL = 50 pF; VCC = 3.3 V - 2.7 - ns tPHL propagation delay nA to nY CL = 50 pF; VCC = 3.3 V - 2.9 - ns CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V -8 -pF ICC quiescent supply current outputs disabled; VCC = 3.6 V - 0.13 - mA |
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