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CDC9841DWR 데이터시트(PDF) 1 Page - Texas Instruments |
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CDC9841DWR 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 9 page CDC9841 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS SCAS458D – DECEMBER 1994 – REVISED APRIL 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Four CPU Clock Outputs With Programmable Frequency (50 MHz, 60 MHz, and 66 MHz) D Six Clock Outputs at Half-CPU Frequency for PCI D One 24-MHz Clock Output D One 12-MHz Clock Output D Two 14.318-MHz Reference Outputs D All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input D LVTTL-Compatible Inputs and Outputs D Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components D Operates at 3.3 VCC D Distributed VCC and Ground Pins Reduce Switching Noise D Packaged in Plastic Small-Outline Package description The CDC9841 is a high-performance clock synthesizer/driver that generates all required clock signals necessary for a high-performance PC motherboard. The four central processing unit (CPU) clock outputs (PCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. The six peripheral-component-interconnect (PCI) clock outputs (BCLKn) are half the frequency of PCLKn and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, the four fixed-frequency outputs provide a 24-MHz clock (CLK24), a 12-MHz clock (CLK12), and two buffered copies of the 14.318-MHz input reference (REF0, REF1). The CDC9841 generates all output frequencies from a 14.31818-MHz crystal input. A reference clock can be provided at X1 instead of a crystal input. Two phase-lock loops (PLLs) generate the CPU clock frequency and the 24-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The PCI and 12-MHz clock frequencies are derived from the base CPU and 24-MHz clock frequencies, respectively. The PLL circuit can be bypassed in the TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input. Because the CDC9841 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, as well as following any changes to the SELn inputs. PCLKn and BCLKn provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state and are enabled via OE. Copyright © 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC X1 X2 GND OE PCLK0 PCLK1 VCC PCLK2 PCLK3 GND SEL1 SEL0 VCC REF0 REF1 VCC CLK12 CLK24 GND BCLK2 BCLK3 VCC BCLK4 BCLK5 GND BCLK1 BCLK0 DW PACKAGE (TOP VIEW) |
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