 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
AD7401 데이터시트(PDF) 4 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD7401 데이터시트(HTML) 4 Page - Analog Devices |
|
|
4 / 20 page  AD7401 Rev. 0 | Page 4 of 20 TIMING SPECIFICATIONS1 VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted. Table 2. Parameter Limit at TMIN, TMAX Unit Description fMCLKIN2 16 MHz max Master clock input frequency 5 MHz min Master clock input frequency t13 25 ns max Data access time after MCLK rising edge t23 15 ns min Data hold time after MCLK rising edge t3 0.4 × tMCLKIN ns min Master clock low time t4 0.4 × tMCLKIN ns min Master clock high time 1 Sample tested during initial release to ensure compliance. 2 Mark space ratio for clock output is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 200µA IOL 200µA IOH 1.6V TO OUTPUT PIN CL 25pF Figure 2. Load Circuit for Digital Output Timing Specifications MCLKIN MDAT t1 t2 t4 t3 Figure 3. Data Timing |
유사한 부품 번호 - AD7401 |
|
유사한 설명 - AD7401 |
|
|
|
링크 URL |
| 개인정보취급방침 |
| ALLDATASHEET.CO.KR |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
