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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD6654 데이터시트(PDF) 9 Page - Analog Devices |
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AD6654 데이터시트(HTML) 9 Page - Analog Devices |
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9 / 88 page  AD6654 Rev. 0 | Page 9 of 88 TIMING CHARACTERISTICS Table 7. Parameter1, 2, 3 Temp Test Level Min Typ Max Unit CLK TIMING REQUIREMENTS tCLK CLK Period Full IV 10.85 ns tCLKL CLK Width Low Full IV 5.154 0.5 × tCLK ns tCLKH CLK Width High Full IV 5.154 0.5 × tCLK ns INPUT WIDEBAND DATA TIMING REQUIREMENTS tDEXP ↑CLK to EXP[2:0] Delay Full IV 5.98 10.74 ns PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER) tDPREQ ↑PCLK to ↑Px REQ Delay (x = A, B, C) Full IV 1.77 3.86 ns tDPP ↑PCLK to Px[15:0] Delay (x = A, B, C) Full IV 2.07 5.29 ns tDPIQ ↑PCLK to Px IQ Delay (x = A, B, C) Full IV 0.48 5.49 ns tDPCH ↑PCLK to Px CH[2:0] Delay (x = A, B, C) Full IV 0.38 5.35 ns tDPGAIN ↑PCLK to Px Gain Delay (x = A, B, C) Full IV 0.23 4.95 ns tSPA Px ACK to ↑PCLK Setup Time (x = A, B, C) Full IV 4.59 ns tHPA Px ACK to ↑PCLK Hold Time (x = A, B, C) Full IV 0.90 ns PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE) tPCLK PCLK Period Full IV 5.0 ns tPCLKL PCLK Low Period Full IV 1.7 0.5 × tPCLK ns tPCLKH PCLK High Period Full IV 0.7 0.5 × tPCLK ns tDPREQ ↑PCLK to ↑Px REQ Delay (x = A, B, C) Full IV 4.72 8.87 ns tDPP ↑PCLK to Px[15:0] Delay (x = A, B, C) Full IV 4.8 8.48 ns tDPIQ ↑PCLK to Px IQ Delay (x = A, B, C) Full IV 4.83 10.94 ns tDPCH ↑PCLK to Px CH[2:0] Delay (x = A, B, C) Full IV 4.88 10.09 ns tDPGAIN ↑PCLK to Px Gain Delay (x = A, B, C) Full IV 5.08 11.49 ns tSPA Px ACK to ↓PCLK Setup Time (x = A, B, C) Full IV 6.09 ns tHPA Px ACK to ↓PCLK Hold Time (x = A, B, C) Full IV 1.0 ns MISC PINS TIMING REQUIREMENTS tRESET RESET Width Low Full IV 30 ns tDIRP CPUCLK/SCLK to IRP Delay Full V 7.5 ns tSSYNC SYNC(0, 1, 2, 3) to ↑CLK Setup Time Full IV 0.87 ns tHSYNC SYNC(0, 1, 2, 3) to ↑CLK Hold Time Full IV 0.67 ns 1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V, and the VDDIO range of 3.0 V to 3.6 V. 2 CLOAD = 40 pF on all outputs, unless otherwise noted. 3 These timing parameters are derived from the ADC ENC rate with DDC CLK driven directly from ADC DR output. |
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