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11 / 55 page November 15, 2004 Am29LV320D 11 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are ini- tiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The fol- lowing subsections describe each of these oper- ations in further detail. Table 1. Am29LV320D Device Bus Operations Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector Block Protection and Unprotection” on page 17. 3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection” on page 17. If WP#/ACC = VHH, all sectors are unprotected. 4. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word con- figuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE# . T he data I/ O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the sys- tem must drive the CE# and OE# pins to VIL. CE# is the power control and selects the de- vice. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the de- vice outputs array data in words or bytes. Operation CE# OE# WE # RESET # WP#/AC C Addresses (Note 2) DQ0– DQ7 DQ8–DQ15 BYTE # = VIH BYTE# = VIL Read L L H H L/H AIN DOUT DOUT DQ8–DQ14 = High-Z, DQ15 = A-1 Write L H L H (Note 3) AIN (Note 4) (Note 4) Accelerated Program L H L H VHH AIN (Note 4) (Note 4) Standby VCC ± 0.3 V XX VCC ± 0.3 V H X High-Z High-Z High-Z Output Disable L H H H L/H X High-Z High-Z High-Z Reset X X X L L/H X High-Z High-Z High-Z Sector Protect (Note 2) L H L VID L/H SA, A6 = L, A1 = H, A0 = L (Note 4) X X Sector Unprotect (Note 2) LH L VID (Note 3) SA, A6 = H, A1 = H, A0 = L (Note 4) X X Temporary Sector Unprotect XX X VID (Note 3) AIN (Note 4) (Note 4) High-Z |
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