Device

Operating

Temperature Range

Package

MC145193

SEMICONDUCTOR

TECHNICAL DATA

PLL FREQUENCY

SYNTHESIZER

ORDERING INFORMATION

MC145193F

TA = –40 to 85°C

SO–20

F SUFFIX

PLASTIC PACKAGE

CASE 751J

(SO–20)

20

1

PIN CONNECTIONS

Order this document by MC145193/D

120

19

18

17

16

15

14

13

2

3

4

5

6

7

8

(Top View)

REFout

LD

φR

REFin

Output A

VDD

12

9

Test 1

11

10

VCC

VPD

Gnd

PDout

Rx

fin

φV

Din

CLK

ENB

Output B

Test 2

fin

EVALUATION KIT

The MC145193EVK, which contains

hardware and software, is available.

1

MOTOROLA WIRELESS SEMICONDUCTOR

SOLUTIONS – RF AND IF DEVICE DATA

1.1 GHz PLL Frequency

Synthesizer

The MC145193 is recommended for new designs and offers reduced

power consumption. The counters are programmed via a synchronous serial

port which is SPI compatible. The serial port is byte-oriented to facilitate

control via an MCU. Due to the innovative BitGrabber Plus

™ registers, the

MC145193 may be cascaded with other peripherals featuring BitGrabber

Plus without requiring leading dummy bits or address bits in the serial data

stream. In addition, BitGrabber Plus peripherals may be cascaded with

existing BitGrabber

™ peripherals.

The device features a single–ended current source/sink phase detector A

output and a double–ended phase detector B output. Both phase detectors

have linear transfer functions (no dead zones). The maximum current of the

single–ended phase detector output is determined by an external resistor

tied from the Rx pin to ground. This current can be varied via the serial port.

Slew–rate control is provided by a special driver designed for the REFout

pin. This minimizes interference caused by REFout.

This part includes a differential RF input that may be operated in a

single–ended mode. Also featured are on–board support of an external

crystal and a programmable reference output. The R, A, and N counters are

fully programmable. The C register (configuration register) allows the part to

be configured to meet various applications. A patented feature allows the C

register to shut off unused outputs, thereby minimizing system noise and

interference.

In order to have consistent lock times and prevent erroneous data from

being loaded into the counters, on–board circuitry synchronizes the update

of the A register if the A or N counters are loading. Similarly, an update of the

R register is synchronized if the R counter is loading.

The double–buffered R register allows new divide ratios to be presented

to the three counters (R, A, and N) simultaneously.

1.7 mA @ 5.0 V or 1.0 mA @ 3.0 V

Serial Port

Devices

Output A: Totem–Pole (Push–Pull) with Four Output Modes

Output B: Open–Drain

Minimizing Lock Times, Standby Current: 30

µA

Offset Reference PLLs for Fine Resolution or Fast Hopping

BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.

© Motorola, Inc. 2000

Rev 1