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23 / 49 page May 8, 2006 25692A2 Am29BDS643G 21 D A TA SH EE T Table 9. Wait States for Handshaking * In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3Eh). The autoselect function allows the host system to determine whether the flash device is enabled for ha ndsha king. See t he “Auto s elect Co mmand Sequence” section for more information. Enable PS (Power Saving) Mode Command Sequence The Enable PS (Power Saving) Mode command sequence is required to set the device to the PS mode. On power up, the Power Saving mode is disabled. The command sequence consists of two unlock cycles fol- lowed by a command cycle in which the address and data should 555h/70h, respectively. The PS mode remains enabled until the device is hardware reset (either device is powered down or RESET# is asserted low). Sector Lock/Unlock Command Sequence The sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. When the device is first powered up, all sectors are locked. To unlock a sector, the system must write the sector lock/unlock command sequence. Two cycles are first written: addresses are don’t care and data is 60h. During the third cycle, the sector address (SLA) and unlock command (60h) is written, while specifying with address A6 whether that sector should be locked (A6 = VIL) or unlocked (A6 = VIH). After the third cycle, the system can continue to lock or unlock additional cycles, or exit the sequence by writing F0h (reset command). Note that the last two outermost boot sectors can be locked by taking the WP# signal to VIL. Also, if VPP is at VIL all sectors are locked; if the VPP input is at VPP, all sectors are unlocked. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is com- plete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively program- ming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read at any address within the same bank any number of times without ini- tiating another autoselect command sequence. The fol- lowing table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address, and SA represents Conditions at Address Typical No. of Clock Cycles after AVD# Low 40 MHz 54/66 MHz Initial address is even 4 5 Initial address is odd 5 6 Initial address is even, and is at boundary crossing* 67 Initial address is odd, and is at boundary crossing* 78 |
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