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AM29BDS643GT5KVAI 데이터시트(PDF) 29 Page - SPANSION |
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AM29BDS643GT5KVAI 데이터시트(HTML) 29 Page - SPANSION |
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29 / 49 page  May 8, 2006 25692A2 Am29BDS643G 27 D A TA SH EE T RDY: Ready The RDY is a dedicated output that indicates (when at logic low) the system should wait until RDY returns high before expecting the next word of data. RDY functions only while reading data in burst mode. The following conditions cause the RDY output to be low: during the initial access (in burst mode); after the boundary that occurs every 64 words beginning with the 63rd address, 3Eh; and when the clock frequency is less than 6 MHz (in which case RDY is low every third clock). The RDY pin will also switch during status reads if there is a clock signal at the CLK input. If RDY goes low, it indicates that the status data is not yet valid and that the system should wait until RDY returns high. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. Note that OE# must be low during toggle bit status reads. When the operation is com- plete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 4 (toggle bit flowchart), DQ6: Toggle Bit I (description), Figure 17 (toggle bit timing diagram), and Table 11 (compares DQ2 and DQ6). Figure 4. Toggle Bit Algorithm START No Yes Yes DQ5 = 1? No Yes DQ6 = Toggle? No Read Byte (DQ0-DQ7) Address = VA DQ6 = Toggle? Read Byte Twice (DQ 0-DQ7) Adrdess = VA Read Byte (DQ0-DQ7) Address = VA FAIL PASS Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. |
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