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AM41LV3204M ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 3 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
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Am41LV3204M
June 10, 2003
P R E L I M I NARY
GENERAL DESCRIPTION
Am29LV320MT Features
The Am29LV320MT/B is a 32 Mbit, 3.0 volt single
power supply flash memory device organized as
2,097,152 words or 4,194,304 bytes. The device has
an 8/16-bit bus and can be programmed either in the
host system or in standard EPROM programmers.
Word mode data appears on DQ15โ€“DQ0. The device
is designed to be programmed in-system with the
standard 3.0 volt V
CC supply, and can also be pro-
grammed in standard EPROM programmers.
LV320MT/B has an access time of 100 ns. Note that
the access time has a specific operating voltage range
(V
CC) as specified in the Product Selector Guide and
the Ordering Information sections. The device is of-
fered in a 69-ball Fine Pitch BGA.
The devices require only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
Hardware data protection measures include a low
V
CC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The Program
Suspend/Program Resume feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
Th e de vice re du ces po wer con sump tio n in th e
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The Write Protect (WP#) feature protects the top or
bottom two sectors by asserting a logic low on the
WP#/ACC pin. The protected sector will still be pro-
tected even during accelerated programming.
The SecSi
๏ฃช (Secured Silicon) Sector provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.


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