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AM41LV3204M ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - SPANSION

๋ถ€ํ’ˆ๋ช… AM41LV3204M
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
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PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 30119
Rev: A Amendment/+1
Issue Date: June 10, 2003
Refer to AMDโ€™s Website (www.amd.com) for the latest information.
Am41LV3204M
Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash
Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
โ–  Power supply voltage of 2.7 to 3.3 volt
โ–  High Performance
โ€” Access time as fast as 100ns initial 30 ns page Flash
70 ns SRAM
โ–  Package
โ€” 69-Ball FBGA
โ€” 8 x 10 x 1.2 mm
โ–  Operating Temperature
โ€”โ€“40
ยฐC to +85ยฐC
Flash Memory Features
ARCHITECTURAL ADVANTAGES
โ–  Single power supply operation
โ€” 3 V for read, erase, and program operations
โ–  Manufactured on 0.23 ยตm MirrorBit process
technology
โ–  SecSi
๏ฃช (Secured Silicon) Sector region
โ€” 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
โ€” May be programmed and locked at the factory or by
the customer
โ–  Flexible sector architecture
โ€” Sixty-three 32 Kword/64-kbyte sectors
โ€” Eight 4 Kword/8-kbyte boot sectors
โ–  Compatibility with JEDEC standards
โ€” Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
โ–  Minimum 100,000 erase cycle guarantee per sector
โ–  20-year data retention at 125
ยฐC
PERFORMANCE CHARACTERISTICS
โ–  High performance
โ€” 100 ns access time
โ€” 30 ns page read times
โ€” 0.5 s typical sector erase time
โ€” 15 ยตs typical write buffer word programming time:
16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
โ€” 4-word/8-byte page read buffer
โ€” 16-word/32-byte write buffer
โ–  Low power consumption (typical values at 3.0 V, 5
MHz)
โ€” 30 mA typical initial Page read current; 10 mA typical
intra-Page read current
โ€” 50 mA typical erase/program current
โ€” 1 ยตA typical standby mode current
SOFTWARE & HARDWARE FEATURES
โ–  Software features
โ€” Program Suspend & Resume: read other sectors
before programming operation is completed
โ€” Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
โ€” Data# polling & toggle bits provide status
โ€” Unlock Bypass Program command reduces overall
multiple-word programming time
โ€” CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
โ–  Hardware features
โ€” Sector Group Protection: hardware-level method of
preventing write operations within a sector group
โ€” Temporary Sector Unprotect: V
ID-level method of
changing code in locked sectors
โ€” WP#/ACC input:
Write Protect input (WP#) protects top or bottom two
sectors regardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
โ€” Hardware reset input (RESET#) resets device
SRAM Features
โ–  Power dissipation
โ€” Operating: 30 mA maximum
โ€” Standby: 10 ยตA maximum
โ–  CE1s# and CE2s Chip Select
โ–  Power down features using CE1s# and CE2s
โ–  Data retention supply voltage: 1.5 to 3.3 volt
โ–  Byte data control: LB#s (DQ7โ€“DQ0),
UB#s (DQ15โ€“DQ8)


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