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AM49LV4608M ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 3 Page - SPANSION

๋ถ€ํ’ˆ๋ช… AM49LV4608M
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM
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ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 30918
Rev: A Amendment/0
Issue Date: November 5, 2003
Refer to AMDโ€™s Website (www.amd.com) for the latest information.
Am49LV6408M
Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8
Mbit (512K x 16-Bit) pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
โ–  Power supply voltage of 2.7 to 3.3 volt
โ–  High Performance
โ€” Access time as fast as 100ns initial 5 ns page Flash
55 ns pSRAM
โ–  Package
โ€” 69-Ball FBGA
โ€” Look ahead pinout for simple migration
โ€” 8 x 10 x 1.2 mm
โ–  Operating Temperature
โ€”โ€“40
ยฐC to +85ยฐC
Flash Memory Features
ARCHITECTURAL ADVANTAGES
โ–  Single power supply operation
โ€” 3 V for read, erase, and program operations
โ–  Manufactured on 0.23 ยตm MirrorBit process
technology
โ–  SecSi
โ„ข (Secured Silicon) Sector region
โ€” 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
โ€” May be programmed and locked at the factory or by
the customer
โ–  Flexible sector architecture
โ€” One hundred twenty seven 32 Kword sectors
โ€” Eight 4 Kword boot sectors
โ–  Compatibility with JEDEC standards
โ€” Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
โ–  Minimum 100,000 erase cycle guarantee per sector
โ–  20-year data retention at 125
ยฐC
PERFORMANCE CHARACTERISTICS
โ–  High performance
โ€” 100 ns access time
โ€” 35 ns page read times
โ€” 0.5 s typical sector erase time
โ€” 22 ยตs typical write buffer word programming time:
16-word write buffer reduces overall programming
time for multiple-word updates
โ€” 4-word page read buffer
โ€” 16-word write buffer
โ–  Low power consumption (typical values at 3.0 V, 5
MHz)
โ€” 30 mA typical initial Page read current; 10 mA typical
intra-Page read current
โ€” 50 mA typical erase/program current
โ€” 1 ยตA typical standby mode current
SOFTWARE & HARDWARE FEATURES
โ–  Software features
โ€” Program Suspend & Resume: read other sectors
before programming operation is completed
โ€” Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
โ€” Data# polling & toggle bits provide status
โ€” Unlock Bypass Program command reduces overall
multiple-word programming time
โ€” CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
โ–  Hardware features
โ€” Sector Group Protection: hardware-level method of
preventing write operations within a sector group
โ€” Temporary Sector Unprotect: V
ID-level method of
changing code in locked sectors
โ€” WP#/ACC input:
Write Protect input (WP#) protects top or bottom two
sectors regardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
โ€” Hardware reset input (RESET#) resets device
pSRAM Features
โ–  As fast as 55ns access time
โ–  Power dissipation
โ€” Operating: 23 mA maximum
โ€” Standby: 60 ยตA maximum at 3.0 V
โ–  CE1ps# and CE2ps Chip Select
โ–  Power down features using CE1ps# and CE2ps
โ–  Data retention supply voltage: 1.5 to 3.3 volt
โ–  Byte data control: LB#s (DQ7โ€“DQ0),
UB#s (DQ15โ€“DQ8)


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