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S29CD032G0JQAI100 데이터시트(PDF) 73 Page - SPANSION |
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S29CD032G0JQAI100 데이터시트(HTML) 73 Page - SPANSION |
73 / 87 page November 14, 2005 S29CD-G_00_B0 S29CD-G Flash Family 71 Pr el im i n a r y AC Characteristics Figure 18. Synchronous Command Write/Read Timing Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/ RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is enabled in the Configuration Register. Hardware Reset (RESET#) Note: Not 100% tested. Parameter Description Test Setup All Speed Options Unit JEDEC Std. tREADY RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 11 µs tREADY RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH RESET# High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns tAS CLK ADV# Data In Addresses Data OE# Data Out Valid Address WE# IND/WAIT# CE# Valid Address tDS tWP tCES tADVP tADVCS tWCKS tOE tACS tACH tACS tDF tEHQZ tDH tWADVH tADVCH 10 ns tACH tWC |
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