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S71AL016D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 62 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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S71AL016D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 62 Page - SPANSION

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2Mbit Type 1 SRAM
SRAM_Type01_03A0 August 4, 2004
Pr e l i m i n a r y
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Timing Test Conditions
Figure 1. Power Savings with Page Mode (WE# = VIH)
Item
Input Pulse Level
0.1VCC to 0.9 VCC
Input Rise and Fall Time
5ns
Input and Output Timing Reference Levels
0.5 VCC
Output Load
CL = 30pF
Operating Temperature
-40 to +85ยฐC
Page Address (A4 -A16)
OE#
CE1#
CE2
Word Address (A0 -A3)
Open page
Word 1
Word 2
Word 16
...
LB#, UB#


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