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S71AL016M ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 27 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71AL016M
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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S71AL016M ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 27 Page - SPANSION

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February 23, 2005 S71AL016M_M0_A0
S71AL016M
27
Advanc e
Informatio n
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h anytime the device is ready to read array data.
The system can read CFI information at the addresses given in Table 6 on
page 27, Table 7 on page 27, Table 8 on page 28, and Table 9 on page 28. In
word mode, the upper address bits (A7โ€“MSB) must be all zeros. To terminate
reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the au-
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 6 on page 27, Table 7 on page 27,
Table 8 on page 28, and Table 9 on page 28. The system must write the reset
command to return the device to the read/reset mode.
For further information, please refer to the CFI Specification and CFI Publication
100, available online at http://www.amd.com/flash/cfi. Alternatively, contact an
sales office or representative for copies of these documents.
Note: CFI data related to timeouts may differ from actual timeouts of the product. Consult the Ordering the Erase and
Programming Performance table for timeout guidelines.
Table 6. CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string โ€œQRYโ€
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Table 7. System Interface String
Addresses
Data
Description
1Bh
0027h
VCC Min. (write/erase). D7โ€“D4: volt, D3โ€“D0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase). D7โ€“D4: volt, D3โ€“D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0007h
Typical timeout per single word write 2N ยตs
20h
0000h
Typical timeout for Min. size buffer write 2N ยตs (00h = not supported)
21h
000Ah
Typical timeout per individual block erase 2N ms
22h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
0001h
Reserved for future use
24h
0000h
Max. timeout for buffer write 2N times typical (00h = not supported)
25h
0004h
Max. timeout per individual block erase 2N times typical
26h
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)


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