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S71AL016M ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 29 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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February 23, 2005 S71AL016M_M0_A0
S71AL016M
29
Advanc e
Informatio n
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or eras-
ing provides data protection against inadvertent writes (refer to Table 10 on
page 37 and Table 11 on page 43 for command definitions). In addition, the fol-
lowing hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level sig-
nals during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This
protects data during VCC power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the device resets. Subse-
quent writes are ignored until VCC is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a
write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 10 on page 37 and Table 11 on
page 43 define the valid register command sequences. Note that writing incor-
rect address and data values or writing them in the improper sequence may
place the device in an unknown state. A reset command is then required to set
the device for the next operation.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in AC Characteristics on page 47.
Reading Array Data
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the
Erase Suspend mode. The system can read array data using the standard read
4Bh
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Table 9. Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Addresses
Data
Description


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