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S71AL016M ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 38 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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S71AL016M
S71AL016M_M0 A0 February 23, 2005
Advanc e
Informatio n
Write Operation Status
The device provides several bits to determine the status of a write operation:
DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 12 on page 45 and the following
subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each
offer a method for determining whether a program or erase operation is com-
plete or in progress. These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded
Algorithm is in progress or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the final WE# pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7. The system must
provide the program address to read valid status information on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on DQ7 is active for
approximately 1 ยตs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to
the complement/true datum output described for the Embedded Program algo-
rithm: the erase function changes all the bits in a sector to 1; prior to this, the
device outputs the complement, or 0. The system must provide an address
within any of the sectors selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protected, Data# Polling on DQ7 is active for approximately 100 ยตs, then the
device returns to reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects DQ7 changes from the complement to true data, it can
read valid data at DQ7โ€“DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0โ€“DQ6 while Output Enable (OE#) is as-
serted low. Figure 17, on page 52 illustrates this.
Table 12 on page 45 shows the outputs for Data# Polling on DQ7. Figure 7, on
page 39 shows the Data# Polling algorithm.


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