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5 / 68 page February 23, 2005 S71AL016M_00_A0_A0 S71AL016M based MCPs 5 Advance I n f o rmatio n Table of Contents S71AL016M based MCPs ............................. 3 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6 16 Mb Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .7 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 11 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12 S29AL016M .................................................13 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 13 General Description . . . . . . . . . . . . . . . . . . . . . . . . 14 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 1. S29AL016M Device Bus Operations . . . . . . . . . . . . .17 Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . .17 Writing Commands/Command Sequences . . . . . . . . . . . . . . . 18 Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . 18 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2. Sector Address Tables (Model 01, Top Boot Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 3. Sector Address Tables (Model 02, Bottom Boot Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 4. Autoselect Codes (High Voltage Method) . . . . . . . . .22 Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 22 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 1. Temporary Sector Unprotect Operation................... 23 Figure 2. In-System Single High Voltage Sector Protect/ Unprotect Algorithms ........................................................ 24 SecSi (Secured Silicon) Sector Flash Memory Region . . . . . . . 25 Table 5. SecSi Sector Addressing . . . . . . . . . . . . . . . . . . . . .25 Figure 3. SecSi Sector Protect Verify ................................... 26 Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . 26 Table 6. CFI Query Identification String . . . . . . . . . . . . . . . .27 Table 7. System Interface String . . . . . . . . . . . . . . . . . . . . .27 Table 8. Device Geometry Definition . . . . . . . . . . . . . . . . . .28 Table 9. Primary Vendor-Specific Extended Query . . . . . . . . .28 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 30 Word Program Command Sequence . . . . . . . . . . . . . . . . . . . .31 Figure 4. Program Operation .............................................. 32 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 32 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . 33 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . 33 Figure 5. Erase Operation .................................................. 35 Program Suspend/Program Resume Command Sequence . . . 35 Figure 6. Program Suspend/Program Resume ....................... 36 Table 10. Command Definitions . . . . . . . . . . . . . . . . . . . . . .37 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 7. Data# Polling Algorithm ....................................... 39 RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 8. Toggle Bit Algorithm............................................ 42 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . .42 DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 11. Write Operation Status . . . . . . . . . . . . . . . . . . . . 43 Figure 9. Maximum Negative Overshoot Waveform ............... 44 Figure 10. Maximum Positive Overshoot Waveform ............... 44 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 12. CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 11. Test Setup ....................................................... 46 Table 13. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . 46 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .46 Figure 12. Input Waveforms and Measurement Levels ........... 46 Table 14. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 13. Read Operations Timings.................................... 47 Table 15. Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . 48 Figure 14. RESET# Timings ............................................... 48 Figure 15. Program Operation Timings ................................ 50 Figure 16. Chip/Sector Erase Operation Timings ................... 51 Figure 17. Data# Polling Timings (During Embedded Algorithms) .......................................... 52 Figure 18. Toggle Bit Timings (During Embedded Algorithms) .......................................... 52 Figure 19. DQ2 vs. DQ6 for Erase and Erase Suspend Operations................................................. 53 Table 16. Temporary Sector Unprotect . . . . . . . . . . . . . . . . 53 Figure 20. Temporary Sector Unprotect/Timing Diagram........ 53 Figure 21. Sector Protect/Unprotect Timing Diagram............. 54 Table 17. Alternate CD# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 22. Alternate CE# Controlled Write Operation T imings ............................................................................ 56 Table 18. Erase and Programming Performance . . . . . . . . . . 57 Table 19. TSOP Pin and BGA Package Capcitance . . . . . . . . . 57 Type 4 pSRAM .......................................... 59 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description. . . . . . . . . . . . . . . . . . . . . . 59 Product Portfolio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . 60 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 20. DC Electrical Characteristics (Over the Operating Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . .61 AC Test Loads and Waveforms . . . . . . . . . . . . . . .61 Figure 23. AC Test Loads and Waveforms ............................ 61 Table 21. Switching Characteristics . . . . . . . . . . . . . . . . . . . 62 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 63 Figure 24. Read Cycle 1 (Address Transition Controlled) ........ 63 Figure 25. Read Cycle 2 (OE# Controlled)............................ 63 Figure 26. Write Cycle 1 (WE# Controlled)........................... 64 Figure 27. Write Cycle 2 (CE#1 or CE2 Controlled) ............... 65 Figure 28. Write Cycle 3 (WE# Controlled, OE# Low) ............ 66 Figure 29. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) .. 66 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 68 |
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