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S71AL016M ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 55 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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February 23, 2005 S71AL016M_M0_A0
S71AL016M
55
Advanc e
Informatio n
AC Characteristics
Notes:
1. Not 100% tested.
2. See Table 18 on page 57 for more information.
3. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once
programming resumes (that is, the program resume command is written). If the suspend command was issued after tPOLL,
status data is available immediately after programming resumes. See Figure 22, on page 56.
Table 17. Alternate CD# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
90
100
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
90
100
ns
tAVEL
tAS
Address Setup Time
Min
0
ns
tELAX
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
35
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
35
ns
tEHEL
tCPH
CE# Pulse Width High
Min
25
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
18
ยตs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.7
sec
tRH
RESET# High Time Before Write
Min
50
ns
tPOLL
Program Valid Before Status Polling
(Note 3)
Max
4
ยตs


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