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S71AL016M 데이터시트(PDF) 19 Page - SPANSION |
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S71AL016M 데이터시트(HTML) 19 Page - SPANSION |
19 / 68 page February 23, 2005 S71AL016M_M0_A0 S71AL016M 19 Advanc e Informatio n available to the system. ICC4 in the DC Characteristics table represents the auto- matic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the de- vice is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin re- mains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is as- serted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics on page 47 tables for RESET# parameters and to Figure 14, on page 48 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. |
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