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S71GLXXXNC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 65 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71GLXXXNC0
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-chip Product (MCP)
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S71GLXXXNC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 65 Page - SPANSION

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December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
65
Ad vance
Info rmat i o n
Table 10. Device Geometry Definition
Addresses
(x16)
Data
Description
27h
001Ah
0019h
0018h
Device Size = 2N byte
1A = 512 Mb, 19 = 256 Mb, 18 = 128 Mb
28h
29h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0001h
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Dh
2Eh
2Fh
30h
00xxh
000xh
0000h
000xh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FFh, 001h, 0000h, 0002h = 512 Mb
00FFh, 0000h, 0000h, 0002h = 256 Mb
007Fh, 0000h, 0000h, 0002h = 128 Mb
31h
32h
33h
34h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)


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