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S71GLXXXNC0 데이터시트(HTML) 77 Page - SPANSION

부품명 S71GLXXXNC0
상세내용  Stacked Multi-chip Product (MCP)
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S71GLXXXNC0 데이터시트(HTML) 77 Page - SPANSION

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December 15, 2004 S29GLxxxN_MCP_A1
S29GLxxxN MirrorBitTM Flash Family
77
Ad vance
Info rmat i o n
Password Program Command
Password Read Command
Password Unlock Command
The Password Program command permits programming the password that is
used as part of the hardware protection scheme. The actual password is 64-bits
long. There is no special addressing order required for programming the pass-
word. The password is programmed in 8-bit or 16-bit portions. Each
portion requires a Password Program Command.
Once the Password is written and verified, the Password Protection Mode Lock Bit
in the “Lock Register” must be programmed in order to prevent verification. The
Password Program command is only capable of programming “0”s. Programming
a “1” after a cell is programmed as a “0” results in a time-out by the Embedded
Program AlgorithmTM with the cell remaining as a “0”. The password is all F’s when
shipped from the factory. All 64-bit password combinations are valid as a
password.
The Password Read command is used to verify the Password. The Password is
verifiable only when the Password Protection Mode Lock Bit in the “Lock Register”
is not programmed. If the Password Protection Mode Lock Bit in the “Lock Regis-
ter” is programmed and the user attempts to read the Password, the device will
always drive all F’s onto the DQ databus.
The lower two address bits (A1–A0) for word mode and (A1–A-1) for by byte
mode are valid during the Password Read, Password Program, and Password Un-
lock commands. Writing a “1” to any other address bits (AMAX-A2) will
abort the Password Read and Password Program commands.
The Password Unlock command is used to clear the PPB Lock Bit to the “unfreeze
state” so that the PPB bits can be modified. The exact password must be entered
in order for the unlocking function to occur. This 64-bit Password Unlock com-
mand sequence will take at least 2 µs to process each time to prevent a
hacker from running through the all 64-bit combinations in an attempt
to correctly match the password. If another password unlock is issued
before the 64-bit password check execution window is completed, the
command will be ignored. If the wrong address or data is given during
password unlock command cycle, the device may enter the write-to-
buffer abort state. In order to exit the write-to-abort state, the write-to-
buffer-abort-reset command must be given. Otherwise the device will
hang.
The Password Unlock function is accomplished by writing Password Unlock com-
mand and data to the device to perform the clearing of the PPB Lock Bit to the
“unfreeze state”. The password is 64 bits long. A1 and A0 are used for matching.
Writing the Password Unlock command does not need to be address order spe-
cific. An example sequence is starting with the lower address A1-A0=00, followed
by A1-A0=01, A1-A0=10, and A1-A0=11 if the device is configured to operate in
word mode.
Approximately 2 µs is required for unlocking the device after the valid
64-bit password is given to the device. It is the responsibility of the mi-
croprocessor to keep track of the entering the portions of the 64-bit
password with the Password Unlock command, the order, and when to
read the PPB Lock bit to confirm successful password unlock. In order to
re-lock the device into the Password Protection Mode, the PPB Lock Bit Set com-
mand can be re-issued.


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