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S71GLXXXNC0 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 10 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71GLXXXNC0
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-chip Product (MCP)
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10
S71GL512_256_128NC0_00_A0 December 17, 2004
Advan ce
In form ati o n
Input/Output Descriptions
A24-A0
=
25 Address inputs (512 Mb)
A23-A0
=
24 Address inputs (256 Mb)
A22-A0
=
23 Address inputs (128 Mb)
DQ15-DQ0
=
Data input/output
OE#
=
Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE#
=
Write Enable input.
VSS
=
Ground
NC
=
No Connect; not connected internally
RESET#
=
Hardware reset input. Low = device resets and
returns to reading array data
WP#/ACC
=
Hardware write protect input / programming
acceleration input.
CE1#s, CE2s
=
Chip-enable input for pSRAM.
CE#f1
=
Chip-enable input for Flash 1.
VCCf
=
Flash 3.0 Volt-only single power supply.
VCCs
=
pSRAM Power Supply.
UB#s
=
Upper Byte Control (pSRAM).
LB#s
=
Lower Byte Control (pSRAM).
RFU
=
Reserved for future use.
RY/BY#
=
Ready/Busy output.
Logic Symbol
Max+1
16
DQ15โ€“DQ0
AMax*โ€“A0
WE#
WP#/ACC
WE#
RESET#
CE1#s
RY/BY#
UB#
CE2s
OE#
LB#
CE#f1
* AMax = A24 [512 Mb]
= A23 [256 Mb]
= A22 [128 Mb]


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