AD9389A

Rev. 0 | Page 6 of 12

Pin No.

Mnemonic

Type1

Description

1, 48, 49

DVDD

P

1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic

and I/Os. They should be filtered and as quiet as possible.

15, 16, 17

PVDD

P

1.8 V PLL Power Supply. The most sensitive portion of the AD9389A is the clock generation

circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free

power to these pins.

64, Paddle on

Bottom Side

GND

P

Ground. The ground return for all circuitry on-chip. It is recommended that the AD9389A be

assembled on a single, solid ground plane with careful attention given to ground current paths.

36

SDA

C2

Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports

CMOS logic levels from 1.8 V to 3.3 V.

35

SCL

C2

Serial Port Data Clock. This pin serves as the serial port data clock slave for register access.

Supports CMOS logic levels from 1.8 V to 3.3 V.

34

DDCSDA

C2

Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. 5 V CMOS logic level.

33

DDCSCL

C2

Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. 5 V CMOS

logic level.